HW-V5-ML555-G【PDF 60/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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Chapter 3: Hardware Description

R

Serial Bus Clocking with Optional ICS87400 3 -02 Clock Jitter Attenuator

(PCI Express Operation)

By default, the ML555 board connects the PCIE_REFCLK input from the add-in card

connector, through two DC blocking capacitors, and then to GTP X0Y2 MGTREFCLK pins

Y4 and Y3.

The ML555 board layout accommodates end-user installation of an ICS874003-02 PCI

Express Clock Jitter attenuator module as shown in Figure 3-10 . The ICS device should be

installed in board location U16, and series resistors R450 and R451 need to be removed

from the board assembly. Contact Integrated Devices Technology (IDT) for information

and availability of clock jitter attenuator circuits at www.idt.com .

The PCI Express system clock is an ICS874003-02 clock jitter attenuator circuit. The ICS

device has dual LVDS outputs, one of which is connected to GTP_DUAL tile X0Y2

MGTREFCLK and the other is connected to FPGA global clock input pins J16 and J17. The

jitter attenuator can generate either a 100 MHz or a 250 MHz reference clock for the GTP

transceiver and clock management tile (CMT) within the FPGA.

Figure 3-10 shows the connections from the PCI Express connector to the jitter attenuator

and then to the FPGA. The CPLD image provided with the ML555 board by default selects

a 250 MHz reference clock to be generated by the ICS874003-02. Spare I/O from the FPGA

to CPLD could be used to dynamically select different GTP reference clocks to be

generated by the jitter attentuator circuit. Source code for the CPLD design provided with

the ML555 board is included on the CD-ROM.

Clock Jitter

Attenuator

U10 FPGA

P13-A13

P13-A14

PCIE_REFCLK

ICS

874003-02

(U16)

A0

nA0

A1

nA1

PCIE250M_P

PCIE250M_N

PCIE_GCLK_P

PCIE_GCLK_N

Y4

Y3

J16

J17

MGT_REFCLKP

MGT_REFCLKN

GCLKP

GCLKN

GTP X0Y2

CPLD_SPARE3

CPLD

CPLD_SPARE2

CPLD_SPARE1

UG201_c3_09_121006

Figure 3-10:

PCI Express Clocking and Control

Spread spectrum clocking is supported by routing the system board clock into the

transceiver and then generating a local clock for the FPGA design. The external clock from

one GTP_DUAL tile can be used to drive the CLKIN ports of neighboring tiles. A

GTP_DUAL tile shares its clock with its neighbors using dedicated internal clock routing

resources. Refer to the Virtex-5 FPGA RocketIO GTP Transceiver User Guide for additional

information on clocking resources.

60

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

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